Conventional computer systems provide a static view of interrupt priority. Typically, the interrupt priorities are defined by a computer system architect. For example, the system architect determines the priority (or hierarchy) of the interrupts. The determination of interrupt priorities can be time consuming. For instance, during testing of interrupt priorities, the system architect may adjust an interrupt priority numerous times based on a trial and error approach. An incorrect determination of an interrupt priority can negatively impact a computer system. For instance, an incorrectly assigned interrupt priority can cause (or preempt) a high priority interrupt from entering into the system.
In some instances, an operating system needs to maintain strict timing of embedded systems (e.g., modem (4G/5G)) to the network. As such, latency of an interrupt at the hardware level can have significant impact on the timing of embedded systems (e.g., modem (4G/5G)). In conventional computer systems, the operating system is unable to determine how much time an interrupt is waiting at the hardware level before arriving at the central processing unit (CPU). Moreover, in conventional computer systems, the interrupt priority is static and is not able to be automatically adjusted. Accordingly, there is a need to determine how much time an interrupt is waiting at the hardware level before arriving at the CPU. Additionally, there is a need to automatically adjust an interrupt priority based on time values associated with the duration of time an interrupt is waiting at the hardware level.